\documentclass[11pt]{article}
\usepackage{a4}
\usepackage{graphicx}

\oddsidemargin=0pt           % No extra space wasted after first inch.
\evensidemargin=0pt          % Ditto (for two-sided output).
\topmargin=0pt               % Same for top of page.
\headheight=0pt              % Don't waste any space on unused headers.
\headsep=0pt
\textwidth=16cm              % Effectively controls the right margin.
\textheight=24cm

\begin{document}
\title{\bf CALICE ECAL Readout Electronics: VFE-PCB Interface Specification}

\maketitle

\section{Introduction}
The prototype calorimeter will consist of 30 layers of silicon diodes.
Each layer comprises a $3 \times 3$ array of silicon diode wafers, each
containing a $6 \times 6$ array of diodes. Each diode needs to be read out
and so corresponds to a channel. Hence, each wafer contains 36 channels,
each layer contains 
$36 \times 9 = 324$ channels and the whole prototype is 
$324 \times 30 = 9720$ channels.

The silicon
wafers will be mounted onto one very-front-end card (VFE-PCB).
Each VFE-PCB can hold up to 6 wafers in a $2 \times 3$ array. Each
layer will therefore consist of one VFE-PCB fully-populated with 6 wafers
and one VFE-PCB half-populated with 3 wafers in a $1 \times 3$ array.
Because the VFE-PCBs will be physically mounted with alternating
top-bottom orientations, then the 3 wafers in the half-populated
VFE-PCB will be alternating between the two possible $1 \times 3$ arrays.
Hence, there will be 3 different flavours of VFE-PCB; 
fully-populated,
left half-populated and right half-populated.
There are 60 VFE-PCB's in total,
30 fully-populated,
15 left half-populated and 15 right half-populated, with each layer
containing one fully-populated and one half-populated.

The wafers will be read out using 
VFE FLC\_PHY2 chips, each reading 18 channels.
Hence, there will be six or twelve VFE chips per VFE-PCB.
The 18 channels are multiplexed onto a single output line per VFE chip.
The VFE chip will also accept a calibration signal which is used
to inject a pulse at the chip input. 

The interface to the readout elecronics is the connector on the
VFE-PCB which supplies the driving signals for the VFE-PCB and
takes the output signals. The power for the VFE-PCB is supplied
separately.

\section{Signals}
The readout electronics will have an independent ground
from the VFE-PCB's. Hence, all signals on the PCB connector which
provide the interface to the readout electronics
are differential. The connector shield will be grounded at the
VFE-PCB end (? Is this corect? Is it also grounded at the
readout board end?).

Table~\ref{tab:signals} lists the numbers and types of 
signals to and from a fully-populated VFE-PCB.
%
\begin{table}[h]
\begin{center}
\begin{tabular}{||l|c|c|c|c|c|c||}  \hline\hline
Signal & I/O & Type & Specification & Number & Pins & Notes \\ \hline
Sample-and-hold       & In & Digital & Bus LVDS & 1 & 2 & 1 \\
Shift register reset  & In & Digital & Bus LVDS & 1 & 2 & 1 \\
Shift register input  & In & Digital & Bus LVDS & 1 & 2 & 1 \\
Shift register multiplex clock  & In & Digital & Bus LVDS & 1 & 2 & 1 \\
Shift register output & Out & Digital & (Bus?) LVDS & 4? & 8? & 1,2 \\
Channel signal output & Out & Analogue & Differential $0 \pm 1.5$\,V & 12 & 24 & 3,4,5 \\
Calibration timing strobe & In & Digital & Bus LVDS & 1 & 2 & 1,6 \\
Calibration group select & In & Digital & Bus LVDS & 4 & 8 & 1,6 \\
Calibration signal level & In & Analogue & Differential $0 \pm 1.5$\,V & 2 & 4 & 7 \\ \hline
Total & & & & 27 & 54 & \\ \hline \hline
\end{tabular}
\caption{Signals to (``In'') and from (``Out'') the VFE-PCB.}
\label{tab:signals}
\end{center}
\end{table}

\noindent
Notes:
\begin{enumerate}
\item All LVDS signals will have the standard $+1.2$\,V quiescent level.
\item Each of the four shift register output signals are the AND of those
from three of the VFE chips on the VFE-PCB. For half-populated VFE-PCBs,
only two of these output signals will be used.
\item The range of the channel signal output depends on the termination.
The above $\pm 1.5$\,V range assumes $100\,\Omega$
termination within the readout electronics.
\item The twelve channel signal outputs each correspond to the output of
one VFE ship. For half-populated VFE-PCBs,
only six of these channel signal outputs will be used.
\item The channel signal output must be digitised with a 10 bit signal
range, but with 4 bits precision at the low end, rising to 10 bits
precision at the high end. Hence, 14 bits dynamic range, 10 bits precision
is needed.
\item The calibration group select value sets which group of channels
to calibrate. The 18 channels per VFE chip are divided into six groups
of three channels each. These six groups can be selected on either of
the six VFE chips which control a set of three wafers. Hence, there are
twelve groups in total, requiring four bits.
\item The calibration signal level dynamic range and precision
must be at least at good as that for the channel signal output.
\end{enumerate}

\section{Timing}
The time-dependent signals are shown in Fig.~\ref{fig:VfePcbSignals};
the calibration group select lines and signal level are
constant during data capture and transfer.
%
\begin{figure}
\begin{center}
\includegraphics[width=15cm]{VfePcbSignals.eps}
\caption{Time-dependent signals to and from the VFE-PCB.}
\label{fig:VfePcbSignals}
\end{center}
\end{figure}

\noindent
Notes:
\begin{enumerate}
\item The calibration timing strobe is only present if calibrating.
\item The timing between the start of the sequence (given by the rising
edge of the trigger input) or, if calibrating, the rising edge of the
calibration timing strobe, to the sample-and-hold must be accurately
adjustable to $\le 10$ns.
\item The shift register input must overlap with the first shift
register clock. It should go down before the first ADC channel is
sampled.
\item The shift register clock speed must be $\le 5$MHz.
\end{enumerate}

\section{Connectors and cables}
The physical thickness of the VFE-PCB and connector cannot exceed 8mm
due to space contraints. The connector will be the same 68-pin SCSI
as will be used at the readout electronics end.

Each readout board will handle up to eight cables of fully-populated
VFE-PCBs, i.e. $8 \times 12 \times 18 = 1728$ channels.
There will be 16 connectors per board in 8 pairs. Each pair can
be used for one fully-populated VFE-PCB cable or two 
half-populated VFE-PCB cables, one left-handed and one right-handed.

The cable should be twisted pair and around 2m long. There are no
radiation-hard requirements but the cable should meet CERN/DESY specifications
for safety.

Table~\ref{tab:connectors} lists the signals on a fully-populated VFE-PCB connector,
connected to a cable to the bottom readout board connector.
%
\begin{table}[h]
\begin{center}
\begin{tabular}{||c|c|c|c||}  \hline\hline
Connector  & VFE-PCB & \multicolumn{2}{c||}{Readout Board} \\
Pair & Signal & Connector & Link Array \\ \hline
35,1 & OUTPUT1$+$,$-$ & BOT\_AIN$\langle 1..0 \rangle$ & BOT\_ADCIN$\langle 11..10 \rangle$ \\
36,2 & OUTPUT7$+$,$-$ & BOT\_AIN$\langle 3..2 \rangle$ & TOP\_ADCIN$\langle 9..8 \rangle$ \\
37,3 & Unused & \multicolumn{2}{c||}{BOT\_LVDS$\langle 5..4 \rangle$} \\
38,4 & OUTPUT2$+$,$-$ & BOT\_AIN$\langle 5..4 \rangle$ & BOT\_ADCIN$\langle 9..8 \rangle$ \\
39,5 & OUTPUT8$+$,$-$ & BOT\_AIN$\langle 7..6 \rangle$ & TOP\_ADCIN$\langle 11..10 \rangle$ \\
40,6 & HOLD$+$,$-$ & \multicolumn{2}{c||}{BOT\_LVDS$\langle 11..10 \rangle$} \\
41,7 & VCALIB$+$,$-$ & BOT\_AOUT$\langle 1..0 \rangle$ & BOT\_VOUT$\langle 1..0 \rangle$ \\
42,8 & SRIN$+$,$-$ & \multicolumn{2}{c||}{BOT\_LVDS$\langle 15..14 \rangle$} \\
43,9 & RESET$+$,$-$ & \multicolumn{2}{c||}{BOT\_LVDS$\langle 17..16 \rangle$} \\
44,10 & ENABLE1$+$,$-$ & \multicolumn{2}{c||}{BOT\_LVDS$\langle 19..18 \rangle$} \\
45,11 & ENABLE2$+$,$-$ & \multicolumn{2}{c||}{BOT\_LVDS$\langle 21..20 \rangle$} \\
46,12 & ENABLE3$+$,$-$ & \multicolumn{2}{c||}{BOT\_LVDS$\langle 23..22 \rangle$} \\
47,13 & CLOCK$+$,$-$ & \multicolumn{2}{c||}{BOT\_LVDS$\langle 25..24 \rangle$} \\
48,14 & OUTPUT3$+$,$-$ & BOT\_AIN$\langle 9..8 \rangle$ & BOT\_ADCIN$\langle 7..6 \rangle$ \\
49,15 & OUTPUT9$+$,$-$ & BOT\_AIN$\langle 11..10 \rangle$ & TOP\_ADCIN$\langle 5..4 \rangle$ \\
50,16 & ENABLE4$+$,$-$ & \multicolumn{2}{c||}{BOT\_LVDS$\langle 31..30 \rangle$} \\
51,17 & ENABLE5$+$,$-$ & \multicolumn{2}{c||}{BOT\_LVDS$\langle 33..32 \rangle$} \\
52,18 & ENABLE6$+$,$-$ & \multicolumn{2}{c||}{BOT\_LVDS$\langle 35..34 \rangle$} \\
53,19 & Unused & \multicolumn{2}{c||}{BOT\_LVDS$\langle 37..36 \rangle$} \\
54,20 & OUTPUT4$+$,$-$ & BOT\_AIN$\langle 13..12 \rangle$ & BOT\_ADCIN$\langle 5..4 \rangle$ \\
55,21 & OUTPUT10$+$,$-$ & BOT\_AIN$\langle 15..14 \rangle$ & TOP\_ADCIN$\langle 7..6 \rangle$ \\
56,22 & Unused & \multicolumn{2}{c||}{BOT\_LVDS$\langle 43..42 \rangle$} \\
57,23 & Unused & \multicolumn{2}{c||}{BOT\_LVDS$\langle 45..44 \rangle$} \\
58,24 & Unused & \multicolumn{2}{c||}{BOT\_LVDS$\langle 47..46 \rangle$} \\
59,25 & TCALIB1$+$,$-$ & \multicolumn{2}{c||}{BOT\_LVDS$\langle 49..48 \rangle$} \\
60,26 & TCALIB2$+$,$-$ & \multicolumn{2}{c||}{BOT\_LVDS$\langle 51..50 \rangle$} \\
61,27 & Unused & \multicolumn{2}{c||}{BOT\_LVDS$\langle 53..52 \rangle$} \\
62,28 & Unused & \multicolumn{2}{c||}{BOT\_LVDS$\langle 55..54 \rangle$} \\
63,29 & Unused & \multicolumn{2}{c||}{BOT\_LVDS$\langle 57..56 \rangle$} \\
64,30 & OUTPUT5$+$,$-$ & BOT\_AIN$\langle 17..16 \rangle$ & BOT\_ADCIN$\langle 3..2 \rangle$ \\
65,31 & OUTPUT11$+$,$-$ & BOT\_AIN$\langle 19..18 \rangle$ & TOP\_ADCIN$\langle 1..0 \rangle$ \\
66,32 & Unused & \multicolumn{2}{c||}{BOT\_LVDS$\langle 63..62 \rangle$} \\
67,33 & OUTPUT6$+$,$-$ & BOT\_AIN$\langle 21..20 \rangle$ & BOT\_ADCIN$\langle 1..0 \rangle$ \\
68,34 & OUTPUT12$+$,$-$ & BOT\_AIN$\langle 23..22 \rangle$ & TOP\_ADCIN$\langle 3..2 \rangle$ \\ \hline \hline
\end{tabular}
\caption{Signals on fully-populated VFE-PCB connector and cable to bottom readout board connector.}
\label{tab:connectors}
\end{center}
\end{table}

%
\begin{table}[h]
\begin{center}
\begin{tabular}{||c|c|c|c||}  \hline\hline
Connector  & VFE-PCB & \multicolumn{2}{c||}{Readout Board} \\
Pair & Signal & Connector & Link Array \\ \hline
35,1 & OUTPUT1$+$,$-$ & BOT\_AIN$\langle 1..0 \rangle$ & BOT\_ADCIN$\langle 11..10 \rangle$ \\
36,2 & Unused & BOT\_AIN$\langle 3..2 \rangle$ & Unconnected \\
37,3 & Unused & \multicolumn{2}{c||}{BOT\_LVDS$\langle 5..4 \rangle$} \\
38,4 & OUTPUT2$+$,$-$ & BOT\_AIN$\langle 5..4 \rangle$ & BOT\_ADCIN$\langle 9..8 \rangle$ \\
39,5 & Unused & BOT\_AIN$\langle 7..6 \rangle$ & Unconnected \\
40,6 & HOLD$+$,$-$ & \multicolumn{2}{c||}{BOT\_LVDS$\langle 11..10 \rangle$} \\
41,7 & VCALIB$+$,$-$ & BOT\_AOUT$\langle 1..0 \rangle$ & BOT\_VOUT$\langle 1..0 \rangle$ \\
42,8 & SRIN$+$,$-$ & \multicolumn{2}{c||}{BOT\_LVDS$\langle 15..14 \rangle$} \\
43,9 & RESET$+$,$-$ & \multicolumn{2}{c||}{BOT\_LVDS$\langle 17..16 \rangle$} \\
44,10 & ENABLE1$+$,$-$ & \multicolumn{2}{c||}{BOT\_LVDS$\langle 19..18 \rangle$} \\
45,11 & ENABLE2$+$,$-$ & \multicolumn{2}{c||}{BOT\_LVDS$\langle 21..20 \rangle$} \\
46,12 & ENABLE3$+$,$-$ & \multicolumn{2}{c||}{BOT\_LVDS$\langle 23..22 \rangle$} \\
47,13 & CLOCK$+$,$-$ & \multicolumn{2}{c||}{BOT\_LVDS$\langle 25..24 \rangle$} \\
48,14 & OUTPUT3$+$,$-$ & BOT\_AIN$\langle 9..8 \rangle$ & BOT\_ADCIN$\langle 7..6 \rangle$ \\
49,15 & Unused & BOT\_AIN$\langle 11..10 \rangle$ & Unconnected \\
50,16 & ENABLE4$+$,$-$ & \multicolumn{2}{c||}{BOT\_LVDS$\langle 31..30 \rangle$} \\
51,17 & ENABLE5$+$,$-$ & \multicolumn{2}{c||}{BOT\_LVDS$\langle 33..32 \rangle$} \\
52,18 & ENABLE6$+$,$-$ & \multicolumn{2}{c||}{BOT\_LVDS$\langle 35..34 \rangle$} \\
53,19 & Unused & \multicolumn{2}{c||}{BOT\_LVDS$\langle 37..36 \rangle$} \\
54,20 & OUTPUT4$+$,$-$ & BOT\_AIN$\langle 13..12 \rangle$ & BOT\_ADCIN$\langle 5..4 \rangle$ \\
55,21 & Unused & BOT\_AIN$\langle 15..14 \rangle$ & Unconnected \\
56,22 & Unused & \multicolumn{2}{c||}{BOT\_LVDS$\langle 43..42 \rangle$} \\
57,23 & Unused & \multicolumn{2}{c||}{BOT\_LVDS$\langle 45..44 \rangle$} \\
58,24 & Unused & \multicolumn{2}{c||}{BOT\_LVDS$\langle 47..46 \rangle$} \\
59,25 & TCALIB1$+$,$-$ & \multicolumn{2}{c||}{BOT\_LVDS$\langle 49..48 \rangle$} \\
60,26 & TCALIB2$+$,$-$ & \multicolumn{2}{c||}{BOT\_LVDS$\langle 51..50 \rangle$} \\
61,27 & Unused & \multicolumn{2}{c||}{BOT\_LVDS$\langle 53..52 \rangle$} \\
62,28 & Unused & \multicolumn{2}{c||}{BOT\_LVDS$\langle 55..54 \rangle$} \\
63,29 & Unused & \multicolumn{2}{c||}{BOT\_LVDS$\langle 57..56 \rangle$} \\
64,30 & OUTPUT5$+$,$-$ & BOT\_AIN$\langle 17..16 \rangle$ & BOT\_ADCIN$\langle 3..2 \rangle$ \\
65,31 & Unused & BOT\_AIN$\langle 19..18 \rangle$ & Unconnected \\
66,32 & Unused & \multicolumn{2}{c||}{BOT\_LVDS$\langle 63..62 \rangle$} \\
67,33 & OUTPUT6$+$,$-$ & BOT\_AIN$\langle 21..20 \rangle$ & BOT\_ADCIN$\langle 1..0 \rangle$ \\
68,34 & Unused & BOT\_AIN$\langle 23..22 \rangle$ & Unconnected \\
\hline \hline
\end{tabular}
\caption{Signals on left-hand half-populated VFE-PCB connector and cable to bottom 
readout board connector.}
\label{tab:connector2}
\end{center}
\end{table}
%
\begin{table}[h]
\begin{center}
\begin{tabular}{||c|c|c|c||}  \hline\hline
Connector  & VFE-PCB & \multicolumn{2}{c||}{Readout Board} \\
Pair & Signal & Connector & Link Array \\ \hline
1,35 & Unused & TOP\_AIN$\langle 1..0 \rangle$ & Unconnected \\
2,36 & OUTPUT7$+$,$-$ & TOP\_AIN$\langle 3..2 \rangle$ & TOP\_ADCIN$\langle 9..8 \rangle$ \\
3,37 & Unused & \multicolumn{2}{c||}{TOP\_LVDS$\langle 5..4 \rangle$} \\
4,38 & Unused & TOP\_AIN$\langle 5..4 \rangle$ & Unconnected \\
5,39 & OUTPUT8$+$,$-$ & TOP\_AIN$\langle 7..6 \rangle$ & TOP\_ADCIN$\langle 11..10 \rangle$ \\
6,40 & HOLD$+$,$-$ & \multicolumn{2}{c||}{TOP\_LVDS$\langle 11..10 \rangle$} \\
7,41 & VCALIB$+$,$-$ & TOP\_AOUT$\langle 1..0 \rangle$ & TOP\_VOUT$\langle 1..0 \rangle$ \\
8,42 & SRIN$+$,$-$ & \multicolumn{2}{c||}{TOP\_LVDS$\langle 15..14 \rangle$} \\
9,43 & RESET$+$,$-$ & \multicolumn{2}{c||}{TOP\_LVDS$\langle 17..16 \rangle$} \\
10,44 & ENABLE1$+$,$-$ & \multicolumn{2}{c||}{TOP\_LVDS$\langle 19..18 \rangle$} \\
11,45 & ENABLE2$+$,$-$ & \multicolumn{2}{c||}{TOP\_LVDS$\langle 21..20 \rangle$} \\
12,46 & ENABLE3$+$,$-$ & \multicolumn{2}{c||}{TOP\_LVDS$\langle 23..22 \rangle$} \\
13,47 & CLOCK$+$,$-$ & \multicolumn{2}{c||}{TOP\_LVDS$\langle 25..24 \rangle$} \\
14,48 & Unused & TOP\_AIN$\langle 9..8 \rangle$ & Unconnected \\
15,49 & OUTPUT9$+$,$-$ & TOP\_AIN$\langle 11..10 \rangle$ & TOP\_ADCIN$\langle 5..4 \rangle$ \\
16,50 & ENABLE4$+$,$-$ & \multicolumn{2}{c||}{TOP\_LVDS$\langle 31..30 \rangle$} \\
17,51 & ENABLE5$+$,$-$ & \multicolumn{2}{c||}{TOP\_LVDS$\langle 33..32 \rangle$} \\
18,52 & ENABLE6$+$,$-$ & \multicolumn{2}{c||}{TOP\_LVDS$\langle 35..34 \rangle$} \\
19,53 & Unused & \multicolumn{2}{c||}{TOP\_LVDS$\langle 37..36 \rangle$} \\
20,54 & Unused & TOP\_AIN$\langle 13..12 \rangle$ & Unconnected \\
21,55 & OUTPUT10$+$,$-$ & TOP\_AIN$\langle 15..14 \rangle$ & TOP\_ADCIN$\langle 7..6 \rangle$ \\
22,56 & Unused & \multicolumn{2}{c||}{TOP\_LVDS$\langle 43..42 \rangle$} \\
23,57 & Unused & \multicolumn{2}{c||}{TOP\_LVDS$\langle 45..44 \rangle$} \\
24,58 & Unused & \multicolumn{2}{c||}{TOP\_LVDS$\langle 47..46 \rangle$} \\
25,59 & TCALIB1$+$,$-$ & \multicolumn{2}{c||}{TOP\_LVDS$\langle 49..48 \rangle$} \\
26,60 & TCALIB2$+$,$-$ & \multicolumn{2}{c||}{TOP\_LVDS$\langle 51..50 \rangle$} \\
27,61 & Unused & \multicolumn{2}{c||}{TOP\_LVDS$\langle 53..52 \rangle$} \\
28,62 & Unused & \multicolumn{2}{c||}{TOP\_LVDS$\langle 55..54 \rangle$} \\
29,63 & Unused & \multicolumn{2}{c||}{TOP\_LVDS$\langle 57..56 \rangle$} \\
30,64 & Unused & TOP\_AIN$\langle 17..16 \rangle$ & Unconnected \\
31,65 & OUTPUT11$+$,$-$ & TOP\_AIN$\langle 19..18 \rangle$ & TOP\_ADCIN$\langle 1..0 \rangle$ \\
32,66 & Unused & \multicolumn{2}{c||}{TOP\_LVDS$\langle 63..62 \rangle$} \\
33,67 & Unused & TOP\_AIN$\langle 21..20 \rangle$ & Unconnected \\
34,68 & OUTPUT12$+$,$-$ & TOP\_AIN$\langle 23..22 \rangle$ & TOP\_ADCIN$\langle 3..2 \rangle$ \\ \hline \hline
\end{tabular}
\caption{Signals on right-hand half-populated VFE-PCB connector and cable to top
 readout board connector.}
\label{tab:connector3}
\end{center}
\end{table}

%\noindent

\end{document}
