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\begin{document}
\title{\bf CALICE ECAL Readout Electronics: System Overview}

\maketitle

\section{Introduction}

Each layer comprises a $3 \times 3$ array of silicon diode wafers, each
containing a $6 \times 6$ array of diodes. Each diode needs to be read out
and so corresponds to a channel. Hence, each wafer contains 36 channels,
each layer contains 
$36 \times 9 = 324$ channels and the whole prototype is 
$324 \times 30 = 9720$ channels.
The three silicon wafers in a row in each layer
will be mounted on PCB's which route the 
diode signals to the
very front end (VFE) chips which provide amplification and shaping.
Each layer therefore consists of three such VFE-PCB's.
%The schematic structure of one PCB is shown in Fig.~\ref{fig:layer}.
%%
%\begin{figure}
%\begin{center}
%\includegraphics[width=14cm]{layer.eps}
%\caption{Schematic of one row of three silicon wafers mounted on a PCB
%with 6 VFE chips.}
%\label{fig:layer}
%\end{center}
%\end{figure}
%%

The diodes, VFE chips, VFE-PCB's and their power supplies,
as well as the beam trigger and its logic,
will be provide by non-UK
groups, while the UK will need to provide all the 
readout electronics downstream and the data acquisition
(DAQ) system to read it out.
All signals from each VFE-PCB are assumed to be routed through a single
connector. This will provide the well-defined interface between the
two parts of the electronics. The UK will provide any cables needed
from this connector.


\section{Overview of proposed readout system}
An overview of the proposed ECAL system is shown in Fig.~\ref{fig:overview}.
The system has the cables from the VFE-PCB's connecting
directly to 6U VME boards, with all the necessary readout
electronics on these boards. The system would run triggered and read
out each event before allowing the next trigger to occur. This would
be controlled by a single VME trigger handling board which distributes
the trigger across the backplane. No data
reduction is done in hardware, so all 9720 channels are read out
for each trigger.

The basic unit of the readout is based on the 90 VFE-PCB's. These
each hold 108 channels which are multiplexed onto 6 lines. It would
be convenient to contain the whole system in a single standard
VME crate of 21 slots. Assuming a PCI/VME interface card and a single
width trigger card, this leaves 19 slots for the readout boards.
The obvious division is then 15 readout boards, each handling the signals
from 6 VFE-PCB's, equivalent to 2 of the 30 layers of the calorimeter.
%
\begin{figure}
\begin{center}
\includegraphics[width=12cm]{Overview.eps}
\caption{Overview of the proposed ECAL readout system.}
\label{fig:overview}
\end{center}
\end{figure}

Although the ECAL electronics will fit into a single VME crate, if the
readout boards are also used for the HCAL, then more than one crate
will be needed. Hence, the trigger board needs to be duplicated to
drive a second crate.

A further board may be required for testing the readout boards during
the prototype and production phases. This test board will send and receive
the signals to and from a single readout board using the same
cables as the VFE-PCBs.


\section{Cost}
We assume that we will build 2 prototypes of the readout boards
and for production, we need 15 readout boards plus 5 spares.
The trigger board will need at most 1 prototype board and, for
production, 2 boards plus 1 spare. The test board will
be produced during prototyping and no production of this is needed.

In addition to the purpose built boards, the system also needs
commercially available infrastructure, namely,
a PCI/VME interface card, a VME extender, a high-end PC, some disk storage
and VME crates and power supplies.

All the following prices include VAT.
A VME-PCI8026 PCI/VME interface card set, including a 2m cable,
is quoted by National Instruments at \pounds 3889.
A VXI-MXI-2 extender board, including cable, is quoted at the same
location at \pounds 2755. A dual Pentium-IV, 2 GHz, 2 Gbytes memory PC,
with screen and keyboard, is quoted by Compusys at \pounds 3680.
For disk, a 1.4 Tbytes array spread over 12 IDE disks with RAID 5 redundancy
and a SCSI interface, recently bought by the UCL group, was \pounds 8k.
CERN-specification, Wes V429, 6U VME crates,
including power supplies, are quoted at \pounds 4700.

Therefore, an estimated costing of the readout electronics is:
\begin{itemize}
\item Non-recurring design costs; for all electronics = \pounds 2k.
\item Readout boards; \pounds 2800 per board $\times$ 22 boards = \pounds 62k.
\item Trigger board; \pounds 1200 per board $\times$ 4 boards = \pounds 5k.
\item Test board; \pounds 2900 per board = \pounds 3k.
\item Cables (guesstimated); \pounds 30 per cable $\times$ 100 cables = \pounds 3k.
\item PC and disk; \pounds 4k for the PC, \pounds 8k for 1.4 Tbytes of disk = \pounds 12k.
\item VME interfaces; \pounds 4k for PCI-VME interface, \pounds 3k for VME extender = \pounds 7k.
\item 6U VME crate and power supplies; \pounds 5k per crate
$\times$ 2 crates = \pounds 10k.
\end{itemize}
All values given are in FY02/03 prices and include VAT, so 
the total cost of the equipment for the
project is therefore FY02/03 \pounds 104k.

\section{Schedule}
Table~\ref{tab:milestones} shows the schedule for the 
readout electronics.
%
\begin{table}[h]
\begin{center}
\begin{tabular}{||l|c||}  \hline\hline
Task & Date of completion \\ \hline
Readout electronics CDR & October 2002 \\
Prototype readout board design completed & January 2003 \\
Readout board PDR & February 2003 \\
Prototype readout board layout and fabrication completed & March 2003 \\
Test board design completed & April 2003 \\
Prototype trigger board design completed & April 2003 \\
Trigger board PDR & May 2003 \\
Test board layout and fabrication completed & June 2003 \\
Prototype trigger board layout and fabrication completed & June 2003 \\
Prototype readout board and prototype VFE-PCB tests & July 2003 \\
Prototype readout board testing completed & September 2003 \\
Prototype trigger board testing completed & October 2003 \\
Production readout board design completed & October 2003 \\
Readout board FDR & November 2003 \\
Production trigger board design completed & November 2003 \\
Production readout board layout and fabrication completed & December 2003 \\
Trigger board FDR & December 2003 \\
Production trigger board layout and fabrication completed & January 2004 \\
Production readout board testing completed & March 2004 \\
Production trigger board testing completed & March 2004 \\ \hline\hline
\end{tabular}
\caption{Schedule for the readout electronics.}
\label{tab:milestones}
\end{center}
\end{table}
%
The system needs to be ready for a beam test in April 2004. It therefore
needs to be completed by the end of March 2004. Fabrication, testing and
data acquisition software development
of the full system is likely to require around 6 months, which
sets the end of the readout board
prototype phase to be September 2003. Therefore, the
time to January 2003 will be used to complete the specification
and design of the readout
boards. Full specification
prototype fabrication of these will take place by March 2003 and 
prototype testing will take place over summer 2003.

Hence, prototype costs will be incurred in FY02/03, while
production costs will be incurred in FY03/04.
The prototype
costs will be for some of the
infrastructure (PC, the PCI-VME interface, one VME crate and a few cables),
and two readout boards,
giving a total of \pounds 20k in FY02/03.
The remaining infrastructure
and board production costs, totalling FY02/03 \pounds 84k, will
all be incurred in FY03/04.


\section{Effort}
The readout board is estimated to
require around 18 months of engineering effort
in total; 12 months for the board design and 6 for the FPGA firmware.
We estimate that 12 months of engineering effort will be required
for the design of the test and trigger boards. In addition, 1 month
will be needed for layout and fabrication of each of the prototype
readout board, the production readout board, the test board and
the trigger board.
This is a total of 34 months.

We propose to provide 18 months for
the readout board design effort,
including the FPGA design, and
the test and trigger board design
effort from University staff.
The rest of the effort would then be provided by RAL TD,
with 12 months needed for the rest of the
board designs and 4 months for the layout and fabrication
of all the boards.
This effort will be divided approximately equally between FY02/03 and FY03/04,
which are the two FYs in which the system is being produced.

%Who does what?

\end{document}
