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\begin{document}
\title{\bf CALICE ECAL Readout Electronics: VFE-PCB Interface Specification}

\maketitle

\section{Introduction}
The prototype calorimeter will consist of 30 layers of silicon diodes.
Each layer comprises a $3 \times 3$ array of silicon diode wafers, each
containing a $6 \times 6$ array of diodes. Each diode needs to be read out
and so corresponds to a channel. Hence, each wafer contains 36 channels,
each layer contains 
$36 \times 9 = 324$ channels and the whole prototype is 
$324 \times 30 = 9720$ channels.

Either three or six
wafers are mounted onto one very-front-end card (VFE-PCB).
This contains six or twelve VFE FLC\_PHY1 chips, each reading 18 channels.
The channels are multiplexed onto a single output line per VFE chip.
The VFE chip will also accept a calibration signal which is used
to inject a pulse at the chip input. There are 60 VFE-PCB's in total,
30 with three wafers and 30 with six wafers, with one of each type in
each layer.

The interface to the readout elecronics is the connector on the
VFE-PCB which supplies the driving signals for the VFE-PCB and
takes the output signals. The power for the VFE-PCB is supplied
separately.

\section{Signals}
The readout electronics is assumed to have an independent ground
from the VFE-PCB's. Hence, all signals on the PCB connector which
provide the interface to the readout electronics
are differential.
Table~\ref{tab:signals} lists the signals to and from the VFE-PCB.
%
\begin{table}[h]
\begin{center}
\begin{tabular}{||l|c|c|c|c|c|c||}  \hline\hline
Signal & I/O & Type & Specification & Number & Pins & Notes \\ \hline
Sample-and-hold       & In & Digital & LVDS & 1 & 2 & 1 \\
Shift register reset  & In & Digital & LVDS & 1 & 2 & 1 \\
Shift register input  & In & Digital & LVDS & 1 & 2 & 1 \\
Shift register multiplex clock  & In & Digital & LVDS & 1 & 2 & 1 \\
Shift register output & Out & Digital & LVDS & 4 & 8 & 1,2 \\
Channel signal output & Out & Analogue & Differential $0 \pm 1.5$\,V & 12 & 24 & 3,4,5 \\
Calibration timing strobe & In & Digital & LVDS & 1 & 2 & 1,6 \\
Calibration group select & In & Digital & LVDS & 4 & 8 & 1,6 \\
Calibration signal level & In & Analogue & Differential $0 \pm 1.5$\,V & 2 & 4 & 7 \\ \hline
Total & & & & 27 & 54 & \\ \hline \hline
\end{tabular}
\caption{Signals to (``In'') and from (``Out'') the VFE-PCB.}
\label{tab:signals}
\end{center}
\end{table}

\noindent
Notes:
\begin{enumerate}
\item All LVDS signals will have the standard $+1.2$\,V quiescent level.
\item Each of the four shift register output signals are the AND of those
from three of the VFE chips on the VFE-PCB. For half-populated VFE-PCBs,
only two of these output signals will be used.
\item The range of the channel signal output depends on the termination.
The above $\pm 1.5$\,V range assumes $100\,\Omega$
termination within the readout electronics.
\item The twelve channel signal outputs each correspond to the output of
one VFE ship. For half-populated VFE-PCBs,
only six of these channel signal outputs will be used.
\item The channel signal output must be digitised with a 10 bit signal
range, but with 4 bits precision at the low end, rising to 10 bits
precision at the high end. Hence, 14 bits dynamic range, 10 bits precision
is needed.
\item The calibration group select value sets which group of channels
to calibrate. The 18 channels per VFE chip are divided into six groups
of three channels each. These six groups can be selected on either of
the six VFE chips which control a set of three wafers. Hence, there are
twelve groups in total, requiring four bits.
\item The calibration signal level dynamic range and precision
must be at least at good as that for the channel signal output.
\end{enumerate}

\section{Timing}
The time-dependent signals are shown in Fig.~\ref{fig:VfePcbSignals};
the calibration group select lines and signal level are
constant during data capture and transfer.
%
\begin{figure}
\begin{center}
\includegraphics[width=15cm]{VfePcbSignals.eps}
\caption{Time-dependent signals to and from the VFE-PCB.}
\label{fig:VfePcbSignals}
\end{center}
\end{figure}

\noindent
Notes:
\begin{enumerate}
\item The calibration timing strobe is only present if calibrating.
\item The timing between the start of the sequence (given by the rising
edge of the trigger input) or, if calibrating, the rising edge of the
calibration timing strobe, to the sample-and-hold must be accurately
adjustable to $\le 10$ns.
\item The shift register input must overlap with the first shift
register clock. It should go down before the first ADC channel is
sampled.
\item The shift register clock speed must be $\le 5$MHz.
\end{enumerate}

\section{Connectors and cables}
The physical thickness of the VFE-PCB and connector cannot exceed 8mm
due to space contraints. The proposed connector is the same 68-pin SCSI
as will be used at the readout electronics end.

Each readout board will handle up to eight cables of fully-populated
VFE-PCBs, i.e. $8 \times 12 \times 18 = 1728$ channels.
There will be 16 connectors per board in 8 pairs. Each pair can
be used for one fully-populated VFE-PCB cable or two 
half-populated VFE-PCB cables.

The cable should be twisted pair and around 2m long. There are no
radiation-hard requirements but the cable should meet CERN/DESY specifications
for safety.

\end{document}
