\section{Design and fabrication}
\label{sec:design}

In this paper, we present results from a test sensor
which was designed to investigate a binary ECAL
and to demonstrate the feasibility of this approach.
Because a complete ECAL
for this application would require a total
number of pixels of the order of $10^{12}$, this development has
been named the Tera-Pixel Active Calorimeter (TPAC) sensor.
This paper reports on results from the first two versions of a
test sensor, TPAC~1.0 and 1.1, which were based on a 0.18\,$\mu$m CMOS process.

The use of CMOS structures for light-sensing applications was originally 
proposed in the 1970s and CMOS imaging sensors were implemented in the
1990s~\cite{ref:design:history}.
Numerous recent developments to the 
pixel design and processing, such as the pinned photodiode, 
have achieved high-grade performance in areas such as 
low noise and leakage current. Such performance 
can be applied beyond the commercial imaging domain, and CMOS sensors have 
been demonstrated in many alternative applications including 
%medical X-ray 
%imaging [RT16-17], electron microscopy [RT18], EUV detection for solar 
%observation [RT19], 
%particle physics and nuclear physics [RT12-15].  
particle physics~\cite{ref:design:rt3}.

A key advantage of CMOS imaging is the use of standard CMOS fabrication processes, in which a diverse family of NMOS and PMOS transistors, resistors, capacitors and diodes can be manufactured on the same silicon substrate as the sensitive pixel; hence these sensors are often referred to as Monolithic Active Pixel Sensors (MAPS).  In typical imaging applications this allows 
the integration of the readout electronics and control logic at the edge of the array of imaging pixels, offering a very compact one-chip imaging solution.  
%Commercial demands for more “megapixels” have lead foundries to develop smaller and smaller pixels, and so the number of transistors that are implemented per pixel is generally kept to the minimum 3-transistor or 4-transistor architectures, or as low as 1.5 transistors per pixel [RT5-7] by use of novel structures that share transistors and readout columns between pixels.
Although the requirements for particle physics applications of CMOS sensors share 
many aspects with those for commercial imaging, such as low noise performance, 
the pixel pitch needed is usually larger. For the binary readout ECAL,
pixel sizes of order
100\,$\mu$m are needed~\cite{ref:introduction:decal}. 
This large pixel area provides an opportunity to exploit the full range of 
components 
available in the CMOS process, with the possibility to add significant
amounts of circuitry inside these larger pixels, rather than around the
periphery of the sensor. While these in-pixel components would reduce
the light reaching the sensor for imaging applications, they have no 
effect on the passage of charged particles.

% provided the impact on optical fill-factor and efficiency are acceptable.  With these potential costs to performance in mind, there are a great range of potential benefits for adding in-pixel circuits, such as extension of dynamic range [OPIC5], novel reset schemes [LAS], automatic object or feature location [OPIC2][OPIC3], in-pixel analogue-to-digital conversion [OPIC4], in-pixel storage of multiple analogue samples [FAPS], in-pixel storage of digital data, in-pixel threshold-event timing, and data sparsification [OPIC].   
%
%The CMOS structures used for optical imaging can conveniently also be applied to particle physics applications.  Incident optical photons that reach the silicon epitaxial layer are absorbed and will be converted into an electron hole pair, so the total incident charge generated in the silicon is proportional to the intensity of light that is not obstructed by any metal or transistor structures above. 
%
%In a particle physics application, an incident particle of sufficient energy will deposit some of that energy as a near uniform trail of electron-hole pairs along its path through the silicon.  The ionization rate is largely independent of the type of particle. The energy loss has statistical fluctuations that are described by the Landau curve [RT28], where the Landau peak is the most probable energy loss which is approximately 0.29\,keV/$\mu$m, or 80 electron-hole pairs per micron for silicon.   The high-energy particles will pass through metal routing layers and other components in the pixel such that they will still deposit  signal charge, so the issue of ``fill-factor'' that is important for optical imaging applications is no longer of concern.  CMOS sensors are therefore an ideal technology of choice for particle physics applications such as this one.

%In order to demonstrate the feasibility of this approach
%we designed a test sensor for an electromagnetic calorimeter. 
%This is one of the detector subsystems for a future particle 
%accelerator, the International Linear Collider (ILC). Details 
%of the application can be found elsewhere [17, 18]. A complete 
%detector for this application would require around 30 layers of 
%sensors, covering a total surface of the order of 2000\,m$^2$. Given 
%a pixel pitch of the order of 50\,$\mu$m, this corresponds to a total 
%number of pixels of the order of $10^{12}$, so this development has 
%been named the Tera-Pixel Active Calorimeter (TPAC) sensor. In 
%one of the current designs of the ILC machine, particles would 
%collide with a minimum interval of 189\,ns for a period of time 
%lasting approximately 1\,ms; a so-called ``bunch train''. This 
%is followed by a quiet period of 199\,ms, when the sensor can be 
%read out. In every bunch train, only a small fraction of all pixels 
%are actually hit by particles, and so it is estimated that the noise 
%hit rate would dominate the overall data rate. With a target noise
%hit rate of $10^{-6}$, the data will be very sparse so each pixel needs 
%to be able to process the data, decide if a hit occurred, and only 
%report out when this happens.
%
%In this application, the pixel has to detect so-called Minimum 
%Ionizing Particles (MIPs). When a charged particle traverses a 
%medium, it loses energy at a rate that depends on its speed. The 
%energy loss tends to decrease with increasing energy and then 
%reaches a minimum when the particle starts to be relativistic, 
%i.e. when its energy is of the same order as its rest energy (as 
%given by the mass). If the energy is further increased there is 
%only a slight increase in the energy loss, in the range of 10\%, 
%so one can consider the particle to produce minimum ionization 
%if its energy is sufficiently high. When this is the case, the 
%particle is called a MIP. In particle physics experiments, the 
%typical particle energies are sufficiently high so that most 
%particles behave as MIPs. The energy loss for a MIP is normally 
%much smaller than its energy so that it is convenient to consider 
%that they produce a uniform trail of electron-hole pairs when 
%traversing the medium. The ionization rate is largely independent 
%of the type of particles. The energy loss has statistical 
%fluctuations well described by the so-called Landau curve~\cite{ref:landau}, 
%which has a peak and a tail towards high energy losses. The Landau 
%peak is the most probable energy loss and in silicon its value is 
%approximately 0.29\,keV/$\mu$m. This translates into a most probable 
%number of electron-hole pairs per micron of about 80. 


\subsection{Process technology}
The CMOS silicon substrate comprises a very low resistivity base material, 
over which a P-doped epitaxial layer is grown, generally up to 20\,$\mu$m 
in thickness.  
For the application described here, epitaxial layer thicknesses
of 5 and $12\,\mu$m were used.
The silicon substrate and epitaxial layer are predominantly free of 
electric fields, so any charge that has been deposited in the silicon 
will move randomly by diffusion, with typical carrier lifetimes of 
milliseconds, and will be collected in times of the order of 100\,ns
(see section~\ref{sec:testp}).
A potential barrier exists due to the change in substrate doping 
between the silicon substrate and the epitaxial layer as well
as between the heavily doped P-wells and the epitaxial layer, 
which is sufficient 
to keep the majority of carriers within the epitaxial layer.
Also an electric field forms around the positively biased N-well to
P-epitaxial diode, 
in which a diffusing electron will be swept towards the N-well and 
collected as signal.
Figure~\ref{fig:design:cmos} illustrates the basic principles.
%
\begin{figure}[ht!]
\begin{center}
%\includegraphics[width=7cm]{design/recropped-noDPW-arrows.pdf}
%\includegraphics[width=7cm]{design/32-recropped-arrws.pdf}
\includegraphics[width=16cm]{design/NEW-DPW-DIAGRAMS.pdf}
\caption{\sl 
Conceptual illustration of a
charged particle crossing a CMOS sensor epitaxial layer.
The N-well to P-epitaxial diode at the upper left is the
signal collecting diode.
The one at the upper right encloses a PMOS transistor which is
part of the in-pixel circuitry. Left: the latter is exposed and
so can absorb signal charge, reducing efficiency. Right: the N-well
diode is shielded from
absorbing signal charge by the deep P-well implant between it
and the epitaxial layer, reducing signal loss.
}
\label{fig:design:cmos}
\end{center}
\end{figure}

As stated 
above, the epitaxial layer is the detecting volume where charge
is generated.
A good 
approximation is to consider that the most probable 
total number of electron-hole 
pairs generated by a MIP in silicon is equal to 80 pairs/$\mu$m.
For the 12\,$\mu$m thick 
epitaxial layer used in TPAC~1.0, this corresponds to only about 1000 
electron-hole pairs. 
There will also be some contribution 
to the charge generation from the upper few microns of the substrate
which increases the MIP signal charge to around 1200\,$e^-$. 
However, given that the charge can freely diffuse between pixels, 
the number of charge carriers collected by any single pixel is
smaller. Clearly, 
any further loss, specifically due to charge collection by 
unrelated N-wells, would make the efficient
detection of MIPs in CMOS sensors
very difficult, if not impossible.

Due to diffusion, the signal charge will not necessarily be collected by the 
nearest diode, in which case it continues to diffuse and may be collected 
by a diode in a neighbouring pixel.
In particle physics tracking applications or in imaging sensors
this effect is called ``crosstalk'' and represents an undesirable loss of 
image quality for the latter.
Although this is less of an issue for an ECAL sensor, it will
still degrade the performance in this application and so
the pixel design presented in this paper implements four diodes, 
placed toward the corners of the pixel for optimum crosstalk reduction.
The advantage of this approach is also a reduction in charge collection 
time, as the mean distance to any diode is shorter than the single-diode 
solution at the same pixel pitch.

The structure of a standard PMOS transistor presents difficulties for
use in a pixel design, due to the N-well in which the PMOS device sits.
Such N-wells, tied to a positive potential, are as likely to collect 
diffusing charge as the collecting diode. However, any charge which reaches 
these N-wells will not be collected as signal on the diode, and so this 
behaviour represents an inefficiency in charge collection.
For this reason, commercial CMOS sensors normally only use NMOS transistors 
within the pixel, although this significantly limits the circuit functionality 
that can be implemented.
For a complex pixel design with many PMOS transistors and small collecting 
diodes, this inefficiency could dominate the charge collection and the 
resulting signal size would be too small to resolve over the electronic noise.

To address the problem of inefficiency caused by PMOS transistors in the pixel,
we proposed adding a deep P-well implant to the standard CMOS process.
This high-energy implant creates a heavily P-doped 
beneath the N-well of a PMOS transistor, as shown in 
figure~\ref{fig:design:cmos}.
The potential barrier that forms, much like the boundary between the 
epitaxial layer and the substrate, is again sufficient to keep the majority 
of carriers within the epitaxial layer, and more importantly, from being 
collected by the N-well.
This technique restores the charge collection efficiency of the sensor
to be
close to 100\%, although some minor reduction in the initial signal charge 
will occur, as charge deposited in the small proportion of the epitaxial layer 
that is now occupied by the deep P-well implant will be lost.

For the successful implementation of this project, the deep P-well module was 
implemented in a leading 0.18\,$\mu$m commercial process.  
This fabrication process is called ``Isolated N-well MAPS'' (INMAPS)
and is described
in detail elsewhere~\cite{ref:design:inmaps}.  
The INMAPS process features up to 
six metal layers, precision passive components 
for analogue circuit design, and may be stitched to manufacture sensors up 
to wafer scale.  Whilst for this project a particular commercial partner was 
selected, the technology could be implemented in many modern CMOS processes.
This is an important feature if large-scale production were ever required
for a full-size calorimeter.

The TPAC sensors were manufactured using the INMAPS process, and implemented
deep P-well implants
in the pixels to achieve a high charge collection efficiency.
To further understand the device physics, the same design was manufactured 
with two thicknesses (5\,$\mu$m or 12\,$\mu$m) of the epitaxial layer and 
with or without the deep P-well implant.

\subsection{Overall architecture}
The TPAC sensors comprise a $168\times 168$ pixel array, totalling
28,224 pixels, together with row control logic, on-sensor
SRAM memory banks and I/O circuitry in a $9.7\times 10.5$\,mm$^2$ die.
The sensor has been developed with the ILC application in mind. It
is designed to be sensitive during a ``bunch train'', a short
period of the order of 1\,ms, 
which is subdivided into ``bunch crossings'', typically
with several thousand bunch crossings per train.
This structure is consistent with the proposed ILC operation.
The sensors collect the charge deposited by an incident particle in pixels 
arranged on a 50\,$\mu$m pitch.
This signal is compared with a global threshold and if above threshold,
the bunch crossing time-code and location of the 
pixel ``hit'' is recorded in on-sensor memory for readout 
following the bunch train.
%The physics of the target application are such that real incident particles are extremely rare hence artificial hits caused by electronic noise will dominate the volume of hits that are stored and read out. 

Four different pixel designs have been implemented for evaluation, 
which fall into two distinct architectures, called pre-shape and pre-sample. 
These four designs are arranged in four quadrants of $84 \times 84$
pixels.
All pixels contain four small N-well diodes for charge collection
and these are identical for all four designs.
Pixels may be individually masked, allowing any permutation of single 
pixels to be operated and evaluated.

A common control and readout architecture serves all pixel varieties, 
allowing the sensor to be operated as a whole or as sub-regions.
Rows of 42 pixels share row control logic and SRAM memory, while
columns of 168 such rows form a region which shares data readout.
All four regions multiplex their data for external readout off-sensor.
An overview of the architecture is shown in 
figure~\ref{fig:design:architecture}, together with a photograph of
the TPAC~1.0 sensor.
%
\begin{figure}[ht!]
\begin{center}
\includegraphics[height=5cm]{design/31-recropped.pdf}
\includegraphics[height=5cm]{design/TPAC1_photo.png}
\caption{\sl 
Left: overview of sensor architecture; see text for a
detailed explanation.
Right: photograph of the sensor mounted on its PCB.
The four pixel regions and memory areas are visible within
the central area of the sensor.
}
\label{fig:design:architecture}
\end{center}
\end{figure}


\subsection{Pre-shape pixel}
\label{sec:design:preshape}

The pre-shape pixel is based on a conventional analogue front end for a 
charge-collecting detector and is shown in figure~\ref{fig:design:preshape}.
%
\begin{figure}[ht!]
\begin{center}
%\includegraphics[width=5cm,angle=90]{design/33-pixel-preshape-circuit3.pdf}
\includegraphics[width=14cm]{design/preShapSchem4diodes.jpg}
\caption{\sl 
Pre-shape pixel circuit; see text for a detailed explanation.
}
\label{fig:design:preshape}
\end{center}
\end{figure}

Four diodes are connected to a charge preamplifier, which generates a voltage 
step output in proportion to the collected charge.
A CR-RC shaper circuit with an overall peaking time of around 150\,ns generates a pulse 
output in proportion to the input signal.
Including the further circuit gain, full circuit simulation predicts a gain
of 164\,$\mu$V/$e^-$
with respect to total input charge.
The simulated response of the charge preamplifier to signals of varying
magnitude is shown in figure~\ref{fig:design:preshapemips}.
This signal, along with a local common-mode reference, form the
pseudo-differential inputs to the two-stage comparator.  
%
\begin{figure}[ht!]
\begin{center}
\includegraphics[width=7cm]{design/shaper_1-10mips_B.png}
\caption{\sl 
Simulated pre-shape pixel circuit response as a function of time, for
signals injected at the preamplifier input at
a time corresponding to
10\,$\mu$s on the time axis. 
The circuit response at the comparator input is shown.
The input signals shown 
have various magnitudes up to a maximum of
2500\,$e^-$, in steps of 250\,$e^-$. The input signal shape is
modelled as an exponential rise with a 50\,ns time constant.
Together with the finite preamplifier response speed, this
means the observed signals peak around 200\,ns after the signal
injection time.
}
\label{fig:design:preshapemips}
\end{center}
\end{figure}

Following a charge deposit,
the shaper circuit returns to a stable state after a time
depending on the signal size,
and is then able to respond to another input deposit.
Saturation in the shaper circuit occurs for signal charge deposits greater 
than 2500\,$e^-$, beyond which the shaper output becomes non-linear and takes 
a longer time to return to the steady state.
Non-recoverable saturation of the pixel occurs when the preamplifier 
stage has integrated 10\,k$e^-$ on the diode node, beyond which the gain 
of the pixel deteriorates, reaching 50\% after 22\,k$e^-$,
until it will no longer respond to an input signal.
The preamplifier reset is used to initialise the pixel before the start of a 
bunch train.
The expected incident signal charge for a single pixel during a bunch
train for the ILC ECAL application is small compared to these saturation 
limits.

To achieve high circuit gain in the preamplifier, a small value of the
feedback 
capacitance was required, which was made using two larger capacitors in series 
to comply with manufacturing design rules.
Two different simulation tools, Eldo~\cite{ref:design:eldo} and 
Spectre~\cite{ref:design:spectre},
were used to evaluate the optimum orientation 
of the series feedback capacitors, but the two tools selected different 
topologies for highest gain.
Two capacitor orientations were therefore implemented on the TPAC~1.0 
sensor as 
subtle variants of the pre-shape pixel and these occupy quadrants~0 and 1.
Results from and comparisons of the performance of both quadrants~0 and 1 are
shown in the following sections.

The in-pixel comparator has two stages. The first stage takes two differential 
signals, and produces a real-time differential result, 
with some small analogue signal gain.
The second, high-gain comparator generates the full-swing 
discriminator output, 
and applies an offset trim adjustment with a four-bit resolution.  
The output of the second comparator is enabled with a one-bit mask
which can 
be used to prevent the pixel from generating hit outputs.

Pixels which go above threshold
generate a fixed length pulse using a monostable circuit, the output of
which is connected to row control logic outside the pixel.
The length of the resulting hit output pulse is thus
independent of the signal size.

Electronic circuit noise is estimated at the input to the differential 
comparator and referred back to the diode node using the charge gain.
The dominant noise source is the input transistor of the preamplifier 
circuit; the predicted equivalent noise charge (ENC) for this pixel is
23\,$e^-$.

The nominal power consumption for the pre-shape pixel is 8.9\,$\mu$W during 
operation, although the circuit would be powered off between bunch trains
at the ILC.
Assuming a factor of 100 reduction in power by this method, this is
equivalent to an average power consumption of 36\,$\mu$W/mm$^2$
and hence is is significantly larger than the target power of the analogue 
ECAL designs for the ILC detectors~\cite{ref:design:sid, ref:design:ild}.
However, the main aim of the TPAC~1.0 sensor is to 
investigate the concept of a binary ECAL and demonstrate the feasibility
of the design with a new technology.
Power was regarded as
a secondary issue, at least for this first demonstrator.
Lower power designs will be considered in future versions of the sensor.

%The pre-shape pixel shown in figure~\ref{fig:design:preshape}
%pre-amplifies the collected 
%charge and uses a CR-RC shaper circuit to generate a shaped signal 
%pulse proportional to the input charge as shown in 
%figure~\ref{fig:design:preshapemips}
%A pseudo-differential signal is achieved by using the input to the 
%shaper circuit as a reference level. From the simulation, the signal 
%gain at the input to the comparator is 94\,$\mu$V/$e^-$ and the 
%Equivalent Noise Charge (ENC) is 23\,$e^-$ RMS.
  
%A two-stage comparator generates an asynchronous local hit decision, 
%using a differential global threshold and applying per-pixel trim 
%adjustment that is configured and stored at the beginning of the 
%sensor operation. A monostable circuit is used to generate an output 
%pulse of a controlled length to ensure a single hit is recorded in 
%the logic, independent of the magnitude of the analogue signal. The 
%shaper circuit naturally recovers after a signal pulse and is 
%therefore ready for a subsequent hit after a short delay time 
%proportional to previous signal magnitude.


%Circuit, parameters. 
%
%Mode of operation.
%
%The implementation of the deep P-well implant in the pixel can be seen 
%in Figure 5. As the charge collection is influenced mainly by the 
%N-well and the deep P-well, only these two layers are shown in the 
%figure; they are coloured purple and grey respectively. The boundary 
%of the 50\,$\mu$m pixel is shown by the dotted lines. 
%The pixel contains 
%four charge collecting diodes (the four purple dots), connected 
%together by metal lines. They are kept small to minimize capacitance, 
%and hence maximize charge-to-voltage conversion gain, and in turn 
%minimize the noise. The other N-wells, all protected by the deep 
%P-well, correspond to where the PMOS transistors and other devices 
%sit. The complex pixel circuits have been arranged such that N-wells 
%can be protected with a single symmetrical deep P-well. The four 
%N-well diodes in each pixel remain exposed to the epitaxial substrate, 
%and have been located towards the corners to help improve pixel charge 
%collection based on TCAD device simulations [20].


\subsection{Pre-sample pixel}
\label{sec:design:presample}

The pre-sample pixel architecture is closer to that of
a conventional MAPS optical sensor. It has
in-pixel analogue storage of a reference level, and is 
shown in figure~\ref{fig:design:presample}. This design was found
to perform worse than the pre-shape circuit in initial tests
and testing was stopped
early on to concentrate on the latter. Only pre-shape pixels were
implemented in the next version of the sensor.
Hence although no detailed study of its performance was done,
and hence no pre-sample
results are shown in the rest of this paper, the design is 
described here for completeness.
%
\begin{figure}[ht!]
\begin{center}
%\includegraphics[width=5cm,angle=90]{design/34-pixel-presample-circuit3.pdf}
\includegraphics[width=14cm]{design/preSampSchem4diodes.jpg}
\caption{\sl 
Pre-sample pixel circuit; see text for a detailed explanation.
}
\label{fig:design:presample}
\end{center}
\end{figure}

The pixel diodes are reset and the
reset level is sampled and stored in-pixel
prior to the start of each bunch train.
Charge integrates on the four collecting diodes, causing a small voltage 
step proportional to the collected charge and the node capacitance.
A charge preamplifier provides a
voltage step which, along with the local sample of the reset level, 
forms a pseudo-differential input to the same two-stage comparator
as for the pre-shape design.
The predicted gain of the circuit is 440\,$\mu$V/$e^-$.
The charge amplifier and reference sample must be reset after a hit 
before the pixel can detect another hit;
this is undertaken by the in-pixel logic.    

The simulated response of the circuit to signals of varying
magnitude is shown in figure~\ref{fig:design:presamplemips}.
Saturation in the pre-sample pixel occurs when the diode node has integrated 
64\,k$e^-$, beyond which non-linear operation is expected.
%
\begin{figure}[ht!]
\begin{center}
\includegraphics[width=7cm]{design/sampler_1-10mips_B.png}
\caption{\sl 
Simulated pre-sample pixel circuit response as a function of time to input
signals injected at 
a time corresponding to
10\,$\mu$s on the time axis. 
The input signals shown 
have various magnitudes up to a maximum of
2500\,$e^-$, in steps of 250\,$e^-$. The input signal shape is
modelled as an exponential rise with a 50\,ns time constant.
}
\label{fig:design:presamplemips}
\end{center}
\end{figure}

Similarly to the pre-shape pixel, a small capacitance in the preamplifier 
feedback is made with two capacitors in series.
This gives rise to two subtle variants of the pre-sample pixel, 
again based on results from different simulator tools, and these
occupy quadrants 2 and 3.

The in-pixel comparator stage is common to all pixel architectures, 
but the pre-sample pixel includes an additional monostable circuit 
to generate the self-reset signals that are necessary to reset the 
amplifier and the reference sample in preparation for another input
signal.

Electronic circuit noise is estimated at the input to the differential 
comparator and referred back to the diode node using the charge gain.
The circuit simulation predicts an ENC at this input of 22\,$e^-$. 
The dominant noise sources are the input transistor of the first source 
follower buffer and the input device in the charge amplifier circuit.
However, the overall observed noise when operating the pixel will be
larger by an additional factor of $\sqrt{2}$ 
to account for the uncorrelated sampling nature of this pixel.
This correction needs to be applied to the real-time simulation 
noise level and so predicts an overall noise of 37\,$e^-$.

The nominal power consumption for the pre-sample pixel is 9.3\,$\mu$W 
during operation, although again the circuit would be powered off between 
bunch trains at the ILC.

%The pre-sample pixel pre-amplifies the voltage drop on 
%the diode node, similar to a conventional MAPS, and then uses a 
%charge amplifier to generate a voltage step proportional to the 
%input. The charge amplifier has been previously reset and a voltage 
%sample stored on a local capacitor. This forms the reference for 
%the pseudo-differential signal, which is then compared by the same 
%two-stage comparator as used in the pre-shape pixel. From the 
%simulation, the signal gain at the input to the comparator is 
%440\,$\mu$V/$e^-$ and the ENC is 22\,$e^-$ RMS. 
%Two monostable circuits generate
%a hit output and the necessary signals to reset the charge amplifier 
%and take a new reference sample. After this short self-reset the pixel 
%is then active and will respond to a subsequent hit.

%The pre-shape and pre-sample pixels comprise 160 and 189 transistors 
%respectively, and are laid out on a 50\,$\mu$m pitch. Two variants of 
%both the pre-shape and pre-sample pixel architectures were implemented. 
%In each case the difference lies only with subtle changes to the 
%capacitors in the circuit to optimize signal gain based on circuit 
%simulations.

\subsection{Mask and trim configuration}
Each pixel contains a five-bit SRAM shift register, 
which is used to store a per-pixel trim (four bits) and a mask flag (one bit).
The configuration shift registers are not used while the sensor 
is in active operation,
but these configuration data are programmed during sensor initialisation,
and are held indefinitely in each pixel until the sensor is powered down 
or the data are rewritten.
The configuration data are loaded through a serial interface, 
which shifts single-bit data into each of 168 columns simultaneously,
as illustrated in figure~\ref{fig:design:config}.
Serial data outputs are available at two points to enable data read-back 
for error-rate monitoring.
The data read is destructive, so in normal operation the read-back occurs 
after hits have been collected.
The total configuration memory space on the sensor is 138\,kbits.
%
\begin{figure}[ht!]
\begin{center}
\includegraphics[width=6cm]{design/35-config-load-recropped.pdf}
\caption{\sl 
Overview of logic for configuration data write and readback.
To load, one bit of the configuration data for each column are shifted 
into the register at the top of the diagram. When completed, these
bits are parallel-loaded into the pixels below. This is continued
until all pixel bits are loaded. The previously stored configuration
data are captured in the register at the bottom of the diagram and
read out, allowing a consistency check.
}
\label{fig:design:config}
\end{center}
\end{figure}


\subsection{Pixel layout}
The pre-shape and pre-sample pixel layouts are illustrated in 
figure~\ref{fig:design:layout}.
%
\begin{figure}[ht!]
\begin{center}
\includegraphics[width=6cm]{design/blockdiagramshaperlayoutcropped3.pdf}
\phantom{XXX}
\includegraphics[width=6cm]{design/blockdiagramsamplerlayoutcropped3.pdf}
\caption{\sl 
Pixel layouts; pre-shape (left) and pre-sample (right).
The boxes labelled ``D'' indicate the diode positions.
The nominal borders of the pixels are shown by the
right-angled corners and dotted lines.
%WHAT IS TRIANGLE?
}
\label{fig:design:layout}
\end{center}
\end{figure}
%
The pre-shape pixel comprises 160 transistors, 27 capacitor cells and a 
large polysilicon resistor.
The pre-sample pixel comprises 189 transistors and 34 capacitor cells.
The two pixel architectures use the same diode positions.
The diodes are not located exactly on a 25\,$\mu$m pitch square grid but
were moved slightly towards
the corners of the 50\,$\mu$m pixel. These positions were 
optimised for charge collection using the simulation
described in section~\ref{sec:simulation:sentaurus}.

The sensitive analogue front-end circuits are located in the very centre 
of the pixel with extensive substrate-grounded guard rings for signal 
integrity.
Analogue signals are routed primarily on metal layer 1, 
with some plates of metal layer 2 used where necessary to shield the analogue 
signals from switching signals passing overhead.
The deep P-well layer is added as a symmetrical cross structure which leaves 
only the collecting N-well diodes exposed to the epitaxial layer,
as shown
in figure~\ref{fig:design:dpwLayout}.
%
\begin{figure}[ht!]
\begin{center}
\includegraphics[width=6cm]{design/dpwShaper.png}
\phantom{XXX}
\includegraphics[width=6cm]{design/dpwSampler.png}
\caption{\sl
Pixel deep P-well implant layouts; pre-shape (left) and pre-sample (right).
The orientation is the same as in the previous figure.
%figure~\ref{fig:design:layout}.
The nominal border of the pixel is shown by the dashed lines, so the areas
outside this are part of the eight neighbouring pixels.
The grey shows the deep P-well implant area while the purple shows
the N-well structures. All the N-well regions are protected by deep P-well
implant except for the four signal diodes towards the pixel corners.
}
\label{fig:design:dpwLayout}
\end{center}
\end{figure}

Pixel power supplies are routed on the metal layers 3, 4 and 6 
in horizontal and vertical directions to distribute power in a mesh structure.
The various sub-circuits in each pixel design are mostly powered separately in 
this first sensor, so there are five independent power supplies routed to the 
pixels.
The hit output signals from pixels are routed horizontally along a row on 
metal layer 5, which is fully shielded from the sensitive analogue electronics 
below by the metal layers in between.

\subsection{Row control logic}
The row logic is responsible for monitoring the individual hit outputs from 
a row of 42 pixels and writing details of any hits to local memory.
An external clock defines the timing with which hit signals are sampled.
The hit signal from a pixel is asynchronous, but will have a fixed output pulse
width defined by the in-pixel monostable bias setting.
This pulse length would typically be set to be around 10\% greater than the 
hit sampling period,
which would be matched to the bunch crossing rate of the target 
application, typically 200-400\,ns.
This regime ensures that an asynchronous hit will always be sampled 
by the synchronous logic, with a small probability that it will be sampled 
twice.
This is an acceptable data overhead that allows for a reasonable spread 
in the length of the monostable pulses, with a minimal risk that an entire 
hit pulse occurs between sampling such that the hit is lost.
The sampling of hits uses an alternating (``ping-pong'') circuit 
architecture to ensure 
there is no dead time between samples.

The 42 sampled hit signals are subdivided into seven ``banks'' for most 
efficient processing and storage.
Each bank is selected for inspection
in turn with a three-bit multiplex (MUX) address code.
An OR circuit then tests the six pixel outputs of the bank to see
whether the bank contains any hits.
If so, the six-bit pixel hit pattern and the three-bit MUX
address code are stored,
thus identifying a single location in the full row of 42 pixels.
This is illustrated in figure~\ref{fig:design:rowlogic}.
A feature of this approach is in the case of a dense particle shower, 
for which multiple nearby hits are stored in a single register, rather than 
multiple registers.
The hit-seeking circuits operate at eight times the bunch crossing rate, 
i.e. up to 50\,MHz.
Multiplex signals are gray-coded for reliable high speed operation, 
and the reserved address value 0 deselects all banks for additional testing 
provision. 
%
\begin{figure}[ht!]
\begin{center}
\includegraphics[width=10cm]{design/36-recropped.pdf}
\caption{\sl 
Overview of the row logic for hit storage; see text for details.
}
\label{fig:design:rowlogic}
\end{center}
\end{figure}


\subsection{Data storage}
\label{sec:design:storage}

The row control logic has 19 SRAM registers available for storage of hit data.
A memory controller is implemented to organise the use of these registers, 
such that registers are not overwritten once used, and only those with valid 
data participate in readout.  This memory controller is implemented as a 
bidirectional shift register, with 20 cells.  The memory control register 
initialises with a token in the first position, which enables the first SRAM 
register for write access.  During data write the shift register advances to 
the next position, filling the SRAM registers in order for the first 19 hits.
A further hit in the row then moves the token into a holding cell, 
which raises a global overflow flag indicating the memory full status.
This hit, and any further hits on that row, will be discarded.  

The row control logic may be operated in ``hit override'' mode, whereby the 
result of the OR circuit is ignored and the value of the hit pattern in each 
bank is always stored.  This operating mode fills the memories in less than
three complete cycles of the standard control sequence, and so is intended as 
a test feature.

The 19 SRAM registers occupy the full 50\,$\mu$m row pitch.  
The hit pattern and corresponding MUX address are stored in the first 
9 bits of a register, with a further 13 bits used to store the global 
timestamp code, which is incremented each time hit signals are sampled.
The cross-coupled inverter structure of a SRAM cell ensures the data will 
be held indefinitely provided the cell is powered, so there is no requirement 
to refresh the data and no maximum hold time after which data are corrupted.  

The full TPAC~1.0 sensor comprises four columns of row logic, 
each with 168 rows, hence there are 12,768 SRAM registers of 22 bits each 
in total.
The row control logic and the SRAM register bank occupy a 250\,$\mu$m wide 
region adjacent to the 42 pixels, equivalent to the area of five pixels.
There is no sense circuitry in this region
and, as no deep P-well is added 
here, charge arising from particles that pass through these regions 
will be collected by local N-wells associated with PMOS transistors
in the logic and SRAM.
This charge will not be collected as signal and
the logic and SRAM are therefore insensitive to incident particles.
In addition, an inactive 50\,$\mu$m wide strip
across the centre of the sensor 
corresponding to a single row of pixels,
is used to distribute bias and reference voltages, and to 
re-buffer control signals.
These inactive regions
result in the sensor having an inherent 11\% dead area.


\subsection{Readout}
During readout, the memory controller is switched into the reverse direction 
and clocked once to initialise the token to enable the most recently written 
register for readout.  
A combinational read-enable signal propagates to the first register that has
valid data for readout, and enables the connection to the parallel readout bus.
On each subsequent clock of the memory controller the next valid register is 
selected until no further registers remain, at which point a ``done'' output 
flag is asserted.
The off-sensor control software uses this flag to initiate readout of each 
logic column in turn.

In addition to the 22-bit SRAM registers, a 9-bit ROM cell is activated during 
readout of each row.  These extra cells encode a unique row address that forms 
part of the parallel data bus.

The SRAM and ROM readout is implemented with a current sense amplifier
which was optimised to operate over long distances with minimal read time.
An activated SRAM or ROM cell pulls current from the parallel data bus 
depending on its state, which is sensed by the circuit at the column base.
A total of 31 of these current-sense amplifiers operate in parallel 
to create a 31-bit digital output data word,
which is multiplexed and driven off-sensor with no 
serialization.
The maximum read time from the furthest cell is 150\,ns and
parallel data readout is typically operated at a 5\,MHz rate.
A full sensor readout, in which every register contains valid hit data (such 
as when operating in hit override mode) 
therefore takes approximately 2.6\,ms, and generates 50\,kBytes of data.


\subsection{Pixel test structures and additional test features}
\label{sec:design:test}

In addition to the main design presented above, the TPAC~1.0 sensor has
three pre-sample 
test pixels on the periphery which have been implemented to 
allow access to internal 
nodes for evaluation.
The test pixel designs correspond to both the quadrant~2 and 3 variants 
but also
include additional analogue buffers to monitor internal 
analogue signals in the pixel circuit.
These facilitate evaluation of the 
performance of monostable circuits, comparators, trim adjustment 
of threshold, and the analogue front end circuits for the pre-sample 
pixel architecture. 
The signal pulse and the reset sample are available for two adjacent pixels, 
and the internal differential comparator output is available from one of
these.
A third pixel allows evaluation of other in-pixel circuits, including the 
two monostables and the full comparator chain.
The circuit is shown in
figure~\ref{fig:design:testpresample}.
These test pixels are included at the edge of the main pixel array. Due to
a lack of time before submission, no pre-shaper test pixels were implemented.
However, a pre-shaper test pixel corresponding to the quadrant~1 variant was
included on TPAC~1.1, again with internal signal connections. This is also
shown in figure~\ref{fig:design:testpresample}.
%
\begin{figure}[ht!]
\begin{center}
%\includegraphics[width=5cm,angle=90]{design/41-testpixel-presample-circuit3.pdf}
\includegraphics[width=14cm]{design/preShapeTest.jpg}
\includegraphics[width=14cm]{design/pixTestSchem4diodes.jpg}
\caption{\sl 
Test pixel circuits for pre-shape on TPAC~1.1 (upper) and pre-sample 
on TPAC~1.0 (lower), showing the internal nodes
which are accessible externally.
}
\label{fig:design:testpresample}
\end{center}
\end{figure}

In addition, 
key digital signals, such as control clocks and the least significant bit 
of the multiplex address and time-code are driven off-sensor at the farthest 
point from their initial distribution.
This debug feature allows the timing of critical signals to be evaluated 
during operation.

All bias currents are independent and are generated off-sensor to evaluate the 
performance of sub-circuits in different operating modes.
The two pixel architectures can be operated independently, 
with separate threshold voltage, bias settings and power-down control.


%\subsection{Data storage}
%Memory operation. Dead area. Memory limit.
%
%The hit outputs from 42 pixels are wired across to each section of 
%row logic. The row logic can latch the state of these asynchronous 
%inputs by external control for synchronization with the beam crossing 
%rate, and then begins the processing sequence.
%
%The principle of the hit data storage is to make optimal use of the 
%finite amount of local memory available in each row. Rather than 
%storing each individual hit separately, the row is divided into 
%seven parts, each containing six pixels. Each of the seven 
%sub-sections of the row is interrogated in turn, and the pattern of 
%hits is stored if any are present. This offers a reduction in the 
%number of memory locations used for a high density of co-incident 
%hits, such as a dense particle shower, whilst only using a single 
%memory location for noise hits.
%  The row logic contains 19 SRAM registers which store the global 
%timestamp code, the pattern of hits and the multiplexer address 
%that identifies their location within the full row of 42 pixels. 
%Row addresses are generated by a local ROM such that they appear 
%as part of the readout parallel data word. The memory manager 
%facilitates data write to each register in turn, and selects each 
%of the valid registers during readout. An overflow flag is raised 
%if more than 19 hits are generated in the row, in which case the 
%data corresponding to the first 19 hits that occurred are retained 
%and any subsequent hit data on that row are discarded. The memory 
%manager is implemented as a bi-directional SRAM shift register that 
%selects a single register with one-hot coding.
%
%The row control logic can be operated in an override mode that stores 
%the hit output from every pixel regardless of status. The 13-bit 
%timestamp is generated off-sensor so arbitrary values can be driven 
%during override operation to verify correct SRAM read and write. 


%\subsection{Readout}
%Operation of readout columns. Speed limitations.
%
%
%\subsection{Fabrication and INMAPS}
%  The sensor (Figure 6) was manufactured in the INMAPS process. The 
%design uses 6 metal levels, and both 1.8 and 3.3\,V transistors. 
%Sensors 
%with and without the deep P-well implant were fabricated so that a 
%direct comparison could be made between them.
%
%0.18\,$\mu$m CMOS INMAPS process.


\subsection{DAQ system and operation}
\label{sec:design:daq}

For all the tests described in this paper, the sensor was
mounted on a custom-designed PCB and read out with a
USB-based readout system using a custom software
data acquisition (DAQ) system.

The PCB design was compatible with both TPAC~1.0 and 1.1 sensors. It
included 31 DACs to allow all the bias
voltages and currents for the sensor to be software
controlled. It also held a temperature sensor. Each
PCB was given a unique ID through a dip switch which
could be read out to the DAQ. Below each sensor, a hole 
approximately $8 \times 8$\,mm$^2$ was cut in the PCB to allow 
access to the substrate for use with a laser 
(see section~\ref{sec:pixel:laser}).
An additional notch approximately $1 \times 1$\,mm$^2$ was 
also cut below the test pixel structures, again to allow illumination
by a laser.
The PCB hole left a strip approximately 1\,mm wide for gluing
the sensor to the PCB. Around 20 sensors were mounted on
PCBs and no mechanical failures of this glue joint were found.
Conductive glue was used to allow the substrate to be
optionally grounded.
The sensor required 
% NESW, outer 29, 33, 39, 34, inner 28, 31, 38, 33
265 wirebonds to connect to the PCB.
%The yield was high, with FEW/NONE??? of
%the wirebonds needing to be rebonded on any of the
%sensors mounted.
The PCB is shown in
figure~\ref{fig:design:sensorpcb}.
%
\begin{figure}[ht!]
\begin{center}
\includegraphics[width=8cm]{design/dscn2483.jpg}
\caption{\sl 
Photograph of the PCB used to hold and operate the
sensor. The hole with the sensor mounted on the lower
side is just right of centre.
}
\label{fig:design:sensorpcb}
\end{center}
\end{figure}

Three 64-way flat ribbon cables connected the sensor PCB to a
generic readout board, the USB\_DAQ card, which provided
the USB interface to the computer. The USB\_DAQ card
required firmware specific to the TPAC~1.0 or 1.1 sensor to
generate the required control and timing signals,
as well as the configuration load and readback, and
the data memory readout. 
It also controlled the PCB DAC settings
and performed the temperature and PCB ID readout.

The sensor was operated with fake ``bunch trains'' to mimic
ILC operation. A bunch train consists of a period of data acquisition
where pixel hits are registered and timestamped according to
a ``bunch crossing'' clock.
Following a fixed number of bunch crossings, the data acquisition is
halted and the pixel hits are read out.
The timing structure of the bunch train was controlled
by the USB\_DAQ and was to a large extent under software 
control. For all following measurements, the
operating parameters for the bunch train
used were a 400\,ns period bunch crossing clock 
and a number of bunch crossings up to the
maximum timestamp storable in the memory of 8192.
